Stress Analysis and Temperature Impact of Negative Bias Temperature Instability (NBTI) on a CMOS inverter circuit

Negative Bias Temperature Instability(NBTI) has become an important reliability concern for ultra-scaled Silicon IC technology with significant implications for both analog and digital circuit design. As the Integrated Circuits (IC) density keeps on increasing with the scaling of CMOS devices in each successive technology generation, stress analysis or reliability concerns mainly Negative Bias Temperature Instability (NBTI) becomes a major challenge. Stress Analysis becomes important for any digital circuit as it predicts the life time of the circuit in terms of the degradation of device parameters. NBTI degrades the performance of a PMOS transistor under a negative gate stress. The after effects of NBTI include: (a) threshold voltage increase of PMOS transistor, (b) drain current degradation, and (c) speed degradation. Elevated temperature and the negative gate stress play an important role in degradation of Gate Oxide. Before any circuit design Stress Analysis becomes important for any device in order to get the complete performance of the circuit. Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper basically we have studied the Stress Analysis and the impact of temperature of NBTI on a CMOS inverter circuit.